a) Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly relates to a method for manufacturing an integrated circuit (IC) a or other such semiconductor device having a MOS transistor.
b) Description of the Related Art
The use of a salicide (self-aligned silicide) process is a known method for manufacturing a MOS transistor with an LDD (Lightly Doped Drain) structure having low-resistance source and drain regions. With this method, the size of the source and drain regions has to be increased in circuit areas that require high resistance, such as input/output protection circuits, and this was disadvantageous in terms of raising the integration of the transistor.
In view of this, methods that improve on the salicide process have been proposed for manufacturing a MOS transistor with an LDD structure having high-resistance source and drain regions (see JP-A-Hei 5-3173, for example). FIGS. 21 to 23 illustrate the steps for manufacturing a MOS transistor having high-resistance source and drain regions and a MOS transistor having low-resistance source and drain regions according to this method.
In the step in FIG. 21, a field insulation film 11 having element holes 11a and 11b is formed on the surface of a p type silicon substrate 10, after which gate insulation films 12a and 12b are formed on the surface of the silicon substrate 10 inside the element holes 11a and 11b. A poly-Si (silicon) layer and a WSi (tungsten silicide) layer are deposited successively on the substrate surface, after which the poly-Si and WSi layers are patterned in the desired gate pattern to form gate electrode layers Ga and Gb over the gate insulation films 12a and 12b, respectively. The gate electrode layer Ga comprises the poly-Si layer 13a and WSi layer 14a remaining after the patterning, and the gate electrode layer Gb comprises the poly-Si layer 13b and WSi layer 14b remaining after the patterning.
Next, the surface of the silicon substrate 10 inside the element holes 11a and 11b is selectively doped with n-type impurities using the gate insulation film 12a and the gate electrode layer Ga, the gate insulation film 12b and the gate electrode layer Gb, and the field insulation film 11 as masks, which forms an n-type source region 15s and drain region 15d, and forms an n-type source region 16s and drain region 16d. A silicon oxide film is deposited on the substrate surface as a side spacer material film, after which this side spacer material film is etched to form side spacers 17s and 17d on both side walls of the gate electrode layer Ga, and to form side spacers 18s and 18d on both side walls of the gate electrode layer Gb. The etching treatment here results in the etching of the portions of the gate insulation films 12a and 12b not covered by the gate electrode layers Ga and Gb and the side spacers 17s, 17d, 18s, and 18d, and in the exposure of the source regions 15s and 16s and drain regions 15d and 16d. 
Next, a silicon oxide film is deposited on the substrate surface as an anti-silicide conversion film, after which the anti-silicide conversion film is etched using a resist layer as a mask, which leaves behind an anti-silicide conversion film 19 that covers a first gate component including the gate insulation film 12a, the gate electrode layer Ga, and the side spacers 17s and 17d; a portion Rs of the source region 15s that is adjacent to the first gate component; and a portion Rd of the drain region 15d that is adjacent to the first gate component. After this, a Ti (titanium) film 20 is deposited as a silicide-forming metal film on the substrate surface.
In the step in FIG. 22, after a silicide conversion treatment has been performed, the unreacted portion of the Ti film 20 is removed by etching. As a result, silicide layers 21s, 21d, 22s, and 22d are formed in the source region 15s, the drain region 15d, source region 16s, and the drain region 16d, respectively. No silicide conversion reaction occurs in the WSi layer 14b of the gate electrode layer Gb at this point.
In the step in FIG. 23, the anti-silicide conversion film 19 is removed by etching. The surface of the silicon substrate 10 inside the element holes 11a and 11b is selectively doped with n type impurities via the silicide layers 21s, 21d, 22s, and 22d and using a first gate component including the gate insulation film 12a, the gate electrode layer Ga, and the side spacers 17s and 17d; and a second gate component including the gate insulation film 12b, the gate electrode layer Gb, and the side spacers 18s and 18d; and the field insulation film 11 as masks, which forms an n+ type source region 23s and drain region 23d, and forms an n+ type source region 24s and drain region 24d. 
With the above manufacturing method, as to the MOS transistor formed inside the element hole 11a, no silicide layer is formed on the portion Rs of the source region 23s directly covered by the anti-silicide conversion film 19, or on the portion Rd of the drain region 23d directly covered by the anti-silicide conversion film 19, and both of these portions Rs and Rd are high-resistance components. Meanwhile, as to the MOS transistor formed inside the element hole 11b, since no anti-silicide conversion film such as the film 19 was positioned in either the source region 24s or the drain region 24d, the silicide layers 22s and 22d account for the majority of the source region 24s and the drain region 24d, which means that the source region 24s and the drain region 24d are both low in resistance.
The MOS transistor inside the element hole 11a has high resistance to electrostatic discharge (ESD), and is used for an IC input/output circuit or the like. The MOS transistor inside the element hole 11b, meanwhile, has low resistance to ESD, and is used for an IC internal circuit or the like. With the above manufacturing method, the location where the anti-silicide conversion film 19 is formed may be somewhat out of position due to misalignment during the formation of the resist layer that serves as the etching mask by photolithography. A problem with this is the large amount of variance in the resistance values of the high- and low-resistance components Rs and Rd.
Also, three more steps are required than in an ordinary salicide process, namely, the deposition, patterning, and removal of the anti-silicide conversion film, which is a problem in terms of a greater number of manufacturing steps.
An object of the present invention is to provide a method for manufacturing a semiconductor device, with which a MOS transistor with high ESD resistance can be manufactured at a good yield.
According to one aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of:
(a) providing a substrate having a first silicon region;
(b) forming a gate electrode layer on said first silicon region so that it is divided into a source disposition component and a drain disposition component;
(c) forming an insulating first mask layer in said source disposition component so that said source disposition component is divided into a first source disposition component and a second source disposition component, and forming an insulating second mask layer in said drain disposition component so that said drain disposition component is divided into a first drain disposition component and a second drain disposition component; and
(d) forming a silicide layer over said first and second source disposition components and in said first silicon region located in said first and second drain disposition components, using said first and second mask layers as a mask.
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of:
providing a substrate having on one principal side a silicon region where there will be formed a MOS transistor having one conduction type of channel;
forming on one principal side of the substrate a field insulation film having element holes located in the silicon region;
covering the silicon surface inside the element holes to form a gate insulation film;
forming a gate electrode layer on the gate insulation film so that the element holes are divided into a source disposition component and a drain disposition component;
disposing an insulating first mask layer in the source disposition component so that the source disposition component is divided into a low-concentration source disposition component close to the gate electrode layer, and a source contact disposition component far from the gate electrode layer, and disposing an insulating second mask layer in the drain disposition component so that the drain disposition component is divided into a low-concentration drain disposition component close to the gate electrode layer, and a drain contact disposition component far from the gate electrode layer;
forming a first source and a first drain region with a relatively low impurity concentration corresponding to the low-concentration source disposition component and the low-concentration drain disposition component, respectively, and forming a source contact region and a drain contact region with a relatively low impurity concentration corresponding to the source contact disposition component and the drain contact disposition component, respectively, by selectively introducing impurities that determine the one conduction type onto the silicon surface inside the element holes, using the gate electrode layer laminated to the gate insulation film, the first and second mask layers, and the field insulation film as a mask;
depositing an insulating side spacer material film that covers the gate insulation film, the gate electrode layer, the first and second mask layers, and the field insulation film;
forming first and second side spacers on the side portions facing the first source and first drain regions in the gate electrode layer by subjecting the side spacer material film to an etch-back treatment so that the first and second mask layers remain, while exposing as components intended for silicide conversion the portion of the first source region interposed between the first side spacer and the first mask layer, the portion of the first drain region interposed between the second side spacer and the second mask layer, the portion of the source contact region adjacent to the portion covered by the first mask layer, and the portion of the drain contact region adjacent to the portion covered by the second mask layer;
forming a second source and a second drain region of a relatively high impurity concentration corresponding to the source disposition component and the drain disposition component, respectively, by selectively introducing impurities that determine the one conduction type to the silicon surface inside the element holes, via the first and second mask layers and using the gate insulation film, the gate electrode layer, the gate component including the first and second side spacers, and the field insulation film as a mask; and
using the gate insulation film, the first and second side spacers, the first and second mask layers, and the field insulation film as a mask to perform a silicide conversion treatment in a state in which a silicide-forming metal is in contact with those parts of the first source region, the source contact region, the first drain region, and the drain contact region that are intended for silicide conversion, and then removing the unreacted silicide-forming metal, which results in the formation of first and second source silicide layers in the part of the first source resin intended for silicide conversion and in the part of the source contact region intended for silicide conversion, and in the formation of first and second drain silicide regions in the part of the first drain region intended for silicide conversion and in the part of the drain contact region intended for silicide conversion, which results in the determination of a first resistance component corresponding to the first mask layer between the first and second source silicide layers, and in the determination of a second resistance component corresponding to the second mask layer between the first and second drain silicide layers.
In the source disposition component, the first source region and the source contact region are formed in a self-aligned form in the first mask layer, and in the drain disposition component, the first drain region and the drain contact region are formed in a self-aligned form in the second mask layer. The second source region and the second drain region are then formed corresponding to the source disposition component and the drain disposition component, respectively, by the introduction of impurities via the first and second mask layers. After this, the first and second source silicide layers are formed in a self-aligned form in the first mask layer, and the first and second drain silicide layers are formed in a selfaligned form in the second mask layer, which results in the determination of the first resistance component corresponding to the first mask layer between the first and second source silicide layers, and in the determination of the second resistance component corresponding to the second mask layer between the first and second drain silicide layers.
Therefore, in the formation of the first and second mask layers by selective etching using a resist layer as a mask, even if misalignment of the resist patterning photomask or another such problem causes the position of the first and second mask layers to shift somewhat with respect to the source disposition component and the drain disposition component, this positional variation will result in essentially no variation in the length of the first and second mask layers in the source-drain direction, and in essentially no variation in the resistance of the first and second resistance components. Accordingly, variance in the resistance values of the first and second resistance components can be suppressed.
Also, since the silicide conversion treatment is performed using the first and second mask layers as a mask after high-concentration impurities have been introduced via the first and second mask layers, there is no need to remove the first and second mask layers, so the process is simpler.
In case of using CMOS, since the first and second mask layers are used also for forming LDD structures of a p channel transistor and an n channel transistor, the patterning step is not added and the number of steps does not increase.
Even if the position of the first and second mask layers shifts somewhat with respect to the source disposition component and the drain disposition component in the formation of the first and second mask layers, this positional variation will cause essentially no variation in the resistance of the first and second resistance components, and variance in resistance values can be suppressed. Also, since the first and second mask layers do not need to be removed, fewer steps are entailed by the procedure. As a result, it is possible to manufacture a MOS transistor with high ESD resistance at a good yield.